Verilog Interview Questions with Answers (Verilog HDL)

Verilog is a Hardware Descriptive Language. Here are the Verilog Interview Questions. These interview questions are related to all the aspects of the Verilog language only (Not VHDL nor System Verilog ).

Verilog Interview Questions ( Verilog HDL Interview Questions )

Q1. What are the difference between Task and Function ?
Ans : The difference between task and function are as follows :

Task can call any number of functions or tasks within itselfFunctions can call any number of function within itself.
Task can contain time control statements like delay operators or @posedge stamentsA function does not contain time control statements . It executes in Zero Simulation time
Task cannot return values, but it can have output arguments.A function returns a single value when it is called.

Q2. What is the difference between Blocking and Non blocking assignments?
Ans : The difference between the Blocking and Non Blocking assignments are as follows :

Blocking AssignmentsNon Blocking Assignments
The evaluation of the expression on the RHS is updated to LHS variable autonomously based on the delay.Assignment of RHS to LHS variable to LHS is scheduled to occur when the next evaluation cycle occurs in simulation.
It is recommended to use blocking statements in the combinational always blocksIt is recommended to use non blocking statements in the sequential always blocks.
These statements are represented by “=” operator sign between LHS and RHS.These statements are represented by “<=” operator sign between LHS and RHS.

Q3. What are the difference between the always and initial construct?
Ans : The difference between the always and initial construct are as follows .

Initial constructAlways Construct
It is Non synthesisable construct.It is a Synthesisable Construct.
Execution takes place only once during simulation.Execution continuously repeats from the beginning to the end of the process unless held by wait construct throughout the simulation session.
Example :
reg a,b;
a = 1’b0;
#10 b=1’b1;
Example :
input a;
output b ;
always @(*)

Q4. What are derived parameters ? Tell some of its advantages
Ans : When one or more parameter are used to define another parament, then the result is derived parameter. The advantage of Derived Parameter is that it makes the RTL Code reusable .

Q5. What is “constant propagation” ?
Ans : Constant propagation is a very effective technique for area minimization, since it forces synthesis tool to optimize the logic in both forward and backward directions. Since the area minimisation is achieved using constants, this technique is known as constant propagation.

Q6. Does Verilog supports an (ab) operator?
Ans : Yes Verilog supports the ab operator by using two astrices (**) , back to back.

Q7. What do you understand by casex and casez statements in verilog ?
Ans : case : considers x or as it is.
casex : considers both x and z as don’t care.
casez : considers z as don’t care.

Q8. Explain the terms ‘wire’ and ‘reg’ ?
Ans : “wire” provide the physical connection. They can not store the values.

Reg is used for those variable which are used to store the some values. They are the data storage elements. These values are assigned in always and initial statement.

Q9. What are the functions of $display , $strobe and $monitor ?
Ans :
$strobe :- It display the values of variables or signals at the end of the current simulation time.

$display : – It display the values of variable or signals at the current simulation time.

$monitor : It display the values of a variable or a signal whenever its value changes.

Q10. What do you understand by transport delay?
Ans : Transport Delay : Transport Delay is the delay caused by the wire connected with the Gates . Wire delays the signals that they carry dues to its resistance, inductance and capacitance . Transport Delays is mainly a propagation delay.

Inertial Delay : Inertial Delay is a kind of default delay.

Q11. What do you understand by timescale directive ( 1ns/1ps )in a Verilog code ?
Ans : Time scale directive is compiler directive which is used to calculate simulation time or the delay time .
Example : `timescale 1ns/1ps .Here 1ns represent the time unit ( unit of measurement related to time in the Verilog code ) and 1ps represent the time precision.

Q12. Explain $time used in Verilog ?
Ans : $time is used to get current simulation time .

Q13. What do you understand by Sensitivity list ?
Ans : A sensitivity list is used to identify the change in the signals or the value ( especially when the always statement is executed )

Q14. Find the bug in the below Verilog code ?

input [3:0] in;
output [3:0] out;
assign out = in[0:3];

Ans : The error is in the assign statement , we can’t use the invert ( opposite as assigned when declared) order of the multibit variable .

Q15. What are the rules governing usage of Verilog functions ?
Ans : The following rules govern the usage of Verilog function constructs :-

  • A function can’t have non blocking statements.
  • A function cannot advance simulation time using construct like @, # etc.
  • A function without a range defaults to a one bit reg for the return value.
  • We cannot declare another object with same name as the function in the scope where the function is declared.

Q16. What are the difference between ‘Specparam’ and ‘parameter?
Ans : Difference between Specparam and parameter is given below : –

Specparam can be defined within both Module and specify blockA Parameter must be defined outside the specify block ad within module
Specparam can be assigned using another Specparam or parameter or a combination of both.Parameter cannot be assigned the value of Specparam.
In Specparam, Value is overridden using SDF AnnotationParameter can be overridden during instantiation or using defparam.

Q17. What will be output of the equation ?
assign Y = 4’b1010 & 4’b0110 ;
Ans : Y = 4’b0010

Q18. What will be output of the equation ?
assign Y = 4’b1010 && 4’b0110 ;

Ans : Y= 4’b0001

Q19. What will be the output of the following equation ?
assign Y = &(8’b11110111);
Ans : Y=8’b00000000

Q20. What is the difference between “==” and “===” ?
Ans :
“==” represents logical equality . It tests only 0 and 1. It does not test for x and z.

“===” represents Case equality. It tests all four states 0,1,X and Z.