# alljobs.co.in

Smart Learning Hub

# Verilog Code of Mux 4 to 1 | Multiplexer with RTL design

A Mux or Multiplexer is a combinational circuit that gives output on the basis of the combination of Select lines. Here is the Verilog code ( structural design) of the Multiplexer ( 4 to 1 ) . The RTL Design and waveform is also given with the test bench .

Contents

## Multiplexer

Multiplexer is a combination circuit in digital electronics. A Mux or Multiplexer gives output ( or selects one of the input ) on the basis of the combination of select lines. Multiplexer are very useful in designing a logic circuit. They can connect two or more sources to a single destination.

Multiplexer are also used to implement Boolean functions. A 4 to 1 Mux have 4 inputs and two select lines. The diagram of the 4 to 1 mux is given in figure 1.

## Truth Table of Mux 4 to 1

In a 4 to 1 Mux , I0, I1, I2, I3, are the four inputs and S0, S1 are two select lines . The output is ” Out”. The Truth table for 4 to 1 Mux is given in Table 1 .

## Verilog Code for 4 to 1 Mux ( Multiplexer )

The Verilog Code for the 4 to 1 mux is given below .

### RTL Design

``````// Verilog Code for 4 to 1 Mux

module mux_4_to_1( out ,  i0 , i1 , i2 , i3 , s1 , s0 );
output out;
input i0 , i1 , i2 , i3 ;  // input variables
input s0 , s1 ; // select lines

wire s1n , s0n , y1 , y2 , y3 ;

not G1( s1n, s1) ; // first not gate
not G2( s0n, s2) ; // second not gate

// instantiating and gates

and  G3(y0 , i0 , s1n, s0n);
and  G4(y1 , i1 , s1n, s0);
and  G5(y2 , i2 , s1, s0n);
and  G6(y3 , i3 , s1, s0);

// instantiating or gate

or G7(out , y0, y1, y2, y3);

endmodule
``````

### Test Bench

The test bench check that each combination of select lines connects the appropriate input to the output. The test bench code in Verilog for 4 to 1 mux is given below.

``````// writing test bench code 4 to 1 mux
module test_mux;
reg IN0, IN1 , IN2 , IN3 ;
reg S1, S0;

wire OUTPUT;

//instantiating above mux_4_to_1 module

mux_4_to_1 mux_test( OUTPUT , IN0, IN1 , IN2 , IN3 , S1, S0 );

initial
begin
IN0 = 0 ; IN1 = 0 ; IN2 = 1 ; IN3 = 1;
#5 \$display(" IN0 = %b, IN1= %b, IN2 = %b, IN3 = %b  \n", IN0 , IN1, IN2, IN3 );

S1 = 0 ; S0 = 0 // for selecting I0 as output.
#5 \$display("S1 = &b , S0 = %b , OUTPUT = %b \n", S1, S0, OUTPUT );

#100

S1 = 0 ; S0 = 1 // for selecting I1 as output.
#5 \$display("S1 = &b , S0 = %b , OUTPUT = %b \n", S1, S0, OUTPUT );

#100

S1 = 1 ; S0 = 0 // for selecting I2 as output.
#5 \$display("S1 = &b , S0 = %b , OUTPUT = %b \n", S1, S0, OUTPUT );

#100

S1 = 1 ; S0 = 1 // for selecting I3 as output.
#5 \$display("S1 = &b , S0 = %b , OUTPUT = %b \n", S1, S0, OUTPUT );

#100
end

endmodule

``````

## Output of the Test Bench Simulation

The output of Test bench Simulation is as follow :

``````IN0 = 0 ; IN1 = 0 ; IN2 = 1 , IN3 =1

S1 = 0 , S0 = 0 , OUTPUT = 0

S1 = 0 , S0 = 1 , OUTPUT = 0

S1 = 1 , S0 = 0 , OUTPUT = 1

S1 = 1 , S0 = 1 , OUTPUT = 1``````