In this post, we’ll explore the Verilog code for a 2:1 mux in three different modeling styles: structural, behavioral, and dataflow. We’ll also provide a Testbench for each code to demonstrate its functionality.
2 X 1 Multiplexer
A 2 x 1 multiplexer, also known as a 2:1 mux, is a digital circuit that selects one of two input signals and forwards it to the output based on a select input. It is commonly used in digital systems to select between two different data sources or operations.
The 2:1 mux has two input signals, A and B, and one select input, S. The output, Y, is connected to either A or B based on the value of S. When S is 0, the output is connected to A, and when S is 1, the output is connected to B.
The functionality of a 2:1 mux can be implemented using logic gates such as AND, OR, and NOT gates, as well as with other multiplexing circuits. In Verilog, a 2:1 mux can be designed using different modeling styles, including structural, behavioral, and dataflow.
Truth Table of 2:1 Mux
In this truth table, S represents the select input of the 2:1 mux, and A and B represent the two input signals. Y represents the output of the mux.
| S | OUTPUT |
|---|---|
| 0 | A |
| 1 | B |
Boolean Equation of 2:1 Mux
The Boolean equation for a 2:1 mux can be derived from its truth table. Let’s represent the select input as S, the input signals as A and B, and the output as Y. Using the truth table, we can write the Boolean equation for the output Y as:
Y = (S. B) + (S’. A)
The first term (S.B) represents the case when S is 1, and the output is connected to input B. The second term (S'.A) represents the case when S is 0, and the output is connected to input A.
Verilog Code 2X1 Mux
A Verilog code for a 2:1 mux is a representation of the circuit that selects one of two input signals and forwards it to the output based on a select input. The Verilog code for a 2:1 mux can be implemented using different modeling styles, including structural, behavioral, and dataflow given below
Structural Modeling Verilog Code 2X1 Mux
module mux_2to1_structural (
input S,
input A,
input B,
output Y
);
wire SA, SB;
and gate1(S, A, SA);
and gate2(S, ~A, SB);
and gate3(~S, B, SB);
and gate4(~S, ~B, SA);
or gate5(SA, SB, Y);
endmodule
// Test Bench
module mux_2to1_tb_structural;
reg S, A, B;
wire Y;
mux_2to1_structural uut (.S(S), .A(A), .B(B), .Y(Y));
initial begin
$monitor("S=%b, A=%b, B=%b, Y=%b", S, A, B, Y);
// Test case 1: S=0, A=1, B=0
S = 0;
A = 1;
B = 0;
#10;
// Test case 2: S=1, A=0, B=1
S = 1;
A = 0;
B = 1;
#10;
// Test case 3: S=0, A=0, B=1
S = 0;
A = 0;
B = 1;
#10;
// Test case 4: S=1, A=1, B=0
S = 1;
A = 1;
B = 0;
#10;
$finish;
end
endmodule
Behavioural Modeling Verilog Code 2X1 Mux
module mux_2to1_behavioral (
input S,
input A,
input B,
output Y
);
always @(*) begin
if (S == 0) begin
Y = A;
end
else begin
Y = B;
end
end
endmodule
// Test Bench
module mux_2to1_tb_behavioral;
reg S, A, B;
wire Y;
mux_2to1_behavioral uut (.S(S), .A(A), .B(B), .Y(Y));
initial begin
$monitor("S=%b, A=%b, B=%b, Y=%b", S, A, B, Y);
// Test case 1: S=0, A=1, B=0
S = 0;
A = 1;
B = 0;
#10;
// Test case 2: S=1, A=0, B=1
S = 1;
A = 0;
B = 1;
#10;
// Test case 3: S=0, A=0, B=1
S = 0;
A = 0;
B = 1;
#10;
// Test case 4: S=1, A=1, B=0
S = 1;
A = 1;
B = 0;
#10;
$finish;
end
endmodule
Dataflow Modeling Verilog Code 2X1 Mux
module mux_2to1_dataflow (
input S,
input A,
input B,
output Y
);
assign Y = (S & ~B) | (~S & A);
endmodule
// Test bench
module mux_2to1_tb_dataflow;
reg S, A, B;
wire Y;
mux_2to1_dataflow uut (.S(S), .A(A), .B(B), .Y(Y));
initial begin
$monitor("S=%b, A=%b, B=%b, Y=%b", S, A, B, Y);
// Test case 1: S=0, A=1, B=0
S = 0;
A = 1;
B = 0;
#10;
// Test case 2: S=1, A=0, B=1
S = 1;
A = 0;
B = 1;
#10;
// Test case 3: S=0, A=0, B=1
S = 0;
A = 0;
B = 1;
#10;
// Test case 4: S=1, A=1, B=0
S = 1;
A = 1;
B = 0;
#10;
$finish;
end
endmodule