Implementation of 4 bit Universal Shift Register using Verilog. The Verilog code of main module and Testbench module is provided here with the RTL Design and Waveforms generated.

Universal Shift Register

A Universal Shift Register is a register which can shift its data in both direction i.e. left and right directions. In other Words , a universal shift register is a bidirectional shift register .

A universal shift register is combination of design of bidirectional shift register and a unidirectional shift register with the parallel load provisions.

A universal shift register can perform parallel to serial operation ( first loading parallel input and then shifting.

A universal shift register can also perform serial to parallel operation ( first shifting and then retrieving parallel output .

The desired operation is then specified by a 2 bit control signal.

Types of Shift Register

There are several types of shift registers, each with its own unique characteristics and applications. Here are the most common types of shift registers:

Serial-In, Serial-Out (SISO) Shift Register: This type of shift register has one data input and one data output, both of which are shifted in a serial manner. This type of register is commonly used for data conversion and data transmission applications.

Serial-In, Parallel-Out (SIPO) Shift Register: This type of shift register has one data input and several data outputs. The input data is shifted in a serial manner, and when the shift operation is complete, the data is available at all output pins simultaneously. This type of register is used for applications that require parallel data transfer.

Parallel-In, Serial-Out (PISO) Shift Register: This type of shift register has several data inputs and one data output. The data is loaded in parallel into the register, and then shifted out in a serial manner. This type of register is used for applications that require serial data output from a parallel input.

Parallel-In, Parallel-Out (PIPO) Shift Register: This type of shift register has several data inputs and several data outputs. The data is loaded in parallel into the register, and when the shift operation is complete, the data is available at all output pins simultaneously. This type of register is used for applications that require both parallel data input and output.

Bidirectional Shift Register: This type of shift register can shift data in both directions, from left to right and from right to left. This type of register is used for applications that require both shifting and shifting back of the data.

Universal Shift Register: This type of shift register can perform any of the above operations by using control signals. It can shift data in any direction and perform any of the above operations. This type of register is used for applications that require flexibility in data transfer and manipulation.

Each type of shift register has its own unique characteristics and applications, and choosing the right type of register is essential for the success of any digital circuit design.

Register Operation Control Signals

Advantages of Universal Shift Register

• Universal Shift register can perform three operations
  • shift-left,
  • shift-right, and
  • parallel loading.
•  Universal shift register acts as an interface between one device to another device to transfer the data.

Verilog Code for Universal Shift Register ( 4-bit)

The Verilog code for 4 bit universal shift register is given below:

RTL Design

`timescale 1ns / 1ps
module universal_shift_register (clr,clk,sel,parin,out);
input clr,clk;
input [1:0]sel;
input [3:0]parin;
output reg[3:0]out;

always @(posedge clk)
begin

if(clr)
out=4'b0000;

else
begin
case(sel)
2'b00: out=out;
2'b01: out={parin[0],parin[3:1]};
2'b10: out={parin[2:0],parin[3]};
2'b11: out=parin;
endcase
end

end
endmodule

//testbench
module unsrtb;

reg [3:0]parin;
reg clr;
reg clk;
reg [0:1]sel;
wire [3:0]out;

universal_shift_register uut(.parin(parin),.clr(clr),.clk(clk),.sel(sel),.out(out));

initial  begin 
clk=0;
repeat(100)
#20 clk=~clk;
end

initial  begin
parin=4'b1011;
sel=2'b01;
clr=1'b0;
#40;

parin=4'b1011;
sel=2'b10;
clr=1'b0;
#40;

parin=4'b1011;
sel=2'b11;
clr=1'b0;
#40;

end
endmodule

The Verilog code above represents a Universal Shift Register module that can perform three types of shift operations based on the value of the sel input signal. The three shift operations are left shift, right shift, and parallel load. The module takes four inputs: clr (clear), clk (clock), sel (select), and parin (parallel input), and has one output, out (parallel output).

The timescale 1ns/1ps statement defines the time unit and time precision for the module. In this case, it sets the time unit to 1 nanosecond and time precision to 1 picosecond.

The module declaration starts with the module name, universal_shift_register, and its inputs and outputs enclosed within parentheses. The input ports are clr, clk, sel, and parin, while the output port is out.

The always block is triggered by the positive edge of the clk signal. If the clr input signal is high, the output out is set to 0. If the clr input signal is low, the switch statement is executed based on the value of the sel input signal. If the sel input signal is 2’b00, the output remains the same. If the sel input signal is 2’b01, the output is shifted left with the MSB being replaced by the parin[0] input. If the sel input signal is 2’b10, the output is shifted right with the LSB being replaced by the parin[3] input. If the sel input signal is 2’b11, the output is loaded with the parin input.

The testbench starts with the module name, unsrtb, and defines the input and output signals. The parin input signal takes a 4-bit parallel input, sel input signal takes a 2-bit selection signal, clr input signal takes a 1-bit clear signal, clk input signal takes a 1-bit clock signal, and out output signal takes a 4-bit parallel output. The universal_shift_register module instance is instantiated with the input and output signals.

The initial block starts with the initial keyword and defines the initial values of the input signals. The clock signal is initially set to 0 and toggles every 20 time units for 100 times. After that, the input signals are set to different values for different shift operations.

RTL Schematic Output

The RTL Schematic of the Universal Shift Register is follows :

Output of the Test Bench Simulation

The output of the Test bench simulation ( waveform) is as follow :

Universal Shift Register FAQs