4-bit Sequential Multiplier Verilog and Testbench Code

Implementation of 4 bit Sequential Multiplier Using Verilog . The Verilog and Testbench code of 4 bit Sequential Multiplier is given below.

Sequential multiplier

A Sequential multiplier is one of a design for multiplying two numbers which does include a clock signal and a reset signal. For an n-bit multiplicand and multiplier, the resulting product will be 2n-bits.

Fig 1 : Block Diagram of Sequential Multiplier

In Verilog , there are Various methods to perform multiplication of two 4 bit numbers . Some of them are –

4- bit Sequential Multiplier Verilog Code

The Verilog code for 4- bit Sequential Multiplier is given below:

RTL Design Verilog Code for 4- bit Sequential Multiplier

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module Sequencial_Multiplier (Result, X, A, Clock, c, temp);
input Clock;
input [3:0] A, X;
output reg [7:0] Result;
integer i;
output reg c;
output reg [7:0] temp;
always @ (posedge Clock)
begin
temp [7:0] = 8'b00000000;
for (i =0; i<4; i=i+1)
begin
if(X[i]==0)
begin
{c, temp [7:4]} = temp [7:4] +4'b0000;
temp [7:0] = {c, temp [7:1]};
end
else
begin
{c, temp [7:4]} = temp [7:4] + A;
temp [7:0] = {c, temp [7:1]};
end
end
Result [7:0] = temp [7:0];
end
endmodule

Test Bench Code for 4-bit Sequential Multiplier

The test bench check that each combination of input lines that connects the appropriate input to the output. The test bench code in Verilog for 4-bit Sequential Multiplier is given below :

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module Sequencial_Multiplier_tb ();
reg [3:0] A, X;
reg Clock;
wire [7:0] Result, temp;
wire c;
Sequencial_Multiplier DUT (Result, X, A, Clock, c, temp);
initial
begin
Clock=0;
end
always
#5 Clock=~Clock;
initial
begin
#12 A=4'b0000; X=4'b0000;
#12 A=4'b1010; X=4'b1011;
#12 A=4'b1111; X=4'b1111;
#12 A=4'b1110; X=4'b1000;
#12 A=4'b1001; X=4'b0011;
#20 $stop;
end
endmodule

RTL Schematic Output

The RTL Schematic of the 4 bit Sequential Multiplier is follows :

Output of the Test Bench Simulation

The output of the Test bench simulation ( waveform) is as follow :

4 bit Sequential Multiplier FAQs

Q. Does a sequential Multiplier use a clock ?

Ans. A sequential Multiplier uses a clock.