# Sequence Detector Verilog Code With Test Bench

Implementation of Sequence Detector using Verilog. The Verilog code along with the Testbench code of sequence detectors for the sequence 0101, 0110, 0010, 0011, 1001, 1100,1101,1010,011,010,100 etc is provided below .

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## Sequence Detector

A sequence detector is a sequential state machine which takes an input string of bits and generates an output of one bit . The logic high is produced as output of sequence detector whenever the target sequence has been detected.

## Types of Finite State Machine (FSM)

There are two types of FSM Finite State Machines namely Moore and Mealy Machines.

The Moore Machine is that machine in which the output is dependent only on the present state . The output is independent to inputs. A sequence detector made using the Moore Machine required the ‘n+1’ number of states , where n is the number of bits of sequence to be detected.

The Mealy Machine is that machine in which the output is dependent on both present state of the system and present inputs provided to the machine. A sequence detector made using the Mealy machine requires ‘n’ numbers of state, where n is the number of the bits of the sequence to be detected.

## Concept of Overlapping and Non Overlapping

While creating a sequence detecting machine there are two types of concepts that are to be kept into consideration. These are overlapping and non-overlapping.

### Non-Overlapping Sequence Detection

Lets take an example , Sequence to be detected is 1101.

If the input stream is 1101101101.

Then in the case of Non overlapping the system will generates first ‘one’ at the 4th bit ( sequence is detected at the fourth bits 1101 ).The system then starts fresh to check the sequence. The next sequence is detected at 10th bit.

Input X = 1101101101
Output = 0001000001

### Overlapping Sequence Detection

Let’s again take the same example , Sequence to be detected is 1101.

If the input stream remains same i.e. 1101101101.

Then in the case of the Overlapping, the system generates first ‘one’ at the 4th bit. we see that last bit is 1 in the sequence, and the staring bit in the sequence is also ‘one’ i.e both are same. So the system will consider this bit as the starting bit of next sequence , if sequence is continued in further bits.

In this example , the sequence detector using an overlapping sequence detection method will generate ‘one’ at 4the bit, then at 7th bit and last at 10th bit. It shows that sequence 1101 has been detected thrice in the input bitstream.

Input X = 1101101101
Output = 0001001001

## Sequence Detectors

There are different Sequence Detectors for detecting sequence for detecting 3,4,5 ,etc bits sequence. Some of the common example of the Sequence detectors of 3 bits , 4 bits and 5bits are given below.

## 3bit Sequence Detectors

The below set of sequence detectors consists of the Verilog code of Moore and Mealy Types of 3 bit Sequence Detector with the both Overlapping and Non overlapping sequence detection technique.

• 110 Sequence Detector
• 101 Sequence Detector
• 011 Sequence Detector
• 010 Sequence Detector
• 011 Sequence Detector
• 010 Sequence Detector
• 110 Sequence Detector
• 101 Sequence Detector

## 4bit Sequence Detectors

The below set of sequence detectors consists of the Verilog code of Moore and Mealy Types of 4 bit Sequence Detector with the both Overlapping and Non overlapping sequence detection technique.

## Sequence Detector FAQs

### Q. How many states are required in the ‘n’ bit detection in mealy Machine?

Ans . It will require the ‘n’ number of states for detecting an ‘n’ bit sequence in the input stream of bits.