# HDLBits Solutions Combinational Logic Multiplexers Q61 – Q65

Here are the HDLBits solutions of the question based on the “Multiplexers Q61- Q65” of the combinational Logic section . These solutions will help you to understand better the questions provided on HDL bits platform.

Contents

## Q61. Mux2to1

Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b. Expected solution length: Around 1 line.

``````module top_module(
input a, b, sel,
output out );
assign out = sel?b:a;
endmodule``````

## Q62. Mux2to1v

Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b. Expected solution length: Around 1 line.

``````module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
assign out = sel ? b:a;

endmodule``````

## Q63. Mux9to1v

Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to ‘1’. Expected solution length: Around 15 lines.

``````module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always  @(*)
begin
case (sel)
4'd0: out =a;
4'd1: out =b;
4'd2: out =c;
4'd3: out =d;
4'd4: out =e;
4'd5: out =f;
4'd6: out =g;
4'd7: out =h;
4'd8: out =i;
default : out = 16'hffff;
endcase
end

endmodule``````

## Q64. Mux256to1

Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in, sel=1 selects bits in, sel=2 selects bits in, etc. Expected solution length: Around 1 line.

``````module top_module(
input [255:0] in,
input [7:0] sel,
output out );
always @(*)
begin
for ( integer i=0;i<256;i=i+1)
begin
if ( sel == i )
out = in[i];
end
end

endmodule``````

## Q65. Mux256to1v

Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc. Expected solution length: Around 1–5 lines.

``````module top_module(
input [1023:0] in,
input [7:0] sel,
output [3:0] out );
always @(*)
begin
integer z;
z=0;
for ( integer i=0;i<1024;i=i+4)
begin
if ( sel == z && z<256)
out= {in[i+3],in[i+2],in[i+1],in[i]};
z=z+1;
end
end
endmodule``````