Half adder design and simulation using verilog HDL. The result of simulation and RTL design are also provided.
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Half Adder
Half adder is used to add two single bits. The half adder takes two input of 1 bit each . It generates two outputs – Sum and Carry.
Sum is represented by S and Carry is represented by cout.
Truth Table for Half Adder
| A | B | Sum | Cout |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Half Adder Verilog Code
Dataflow Modelling
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: alljobs.co.in
// Engineer: Team ( alljobs.co.in )
// Design Name: Half Adder
// Module Name: Half Adder
// Project Name: Half Adder using Verilog ( Data Flow Modelling )
// Language Used : Verilog HDL.
// Description: A design of Half adder has been simulated using Verilog HDL.
//////////////////////////////////////////////////////////////////////////////////
module half_adder(a,b,sum,cout);
input a,b;
output sum,cout; // sum and carry
assign sum = a^b;
assign cout = a&b ;
endmodule
//Testbench for halfadder
module half_adder_testbench;
reg a,b;
wire sum,cout;
half_adder h1(a,b,sum,cout);
initial begin
a = 1'b0;
b = 1'b0;
#20;
a = 1'b0;
b = 1'b1;
#20;
a = 1'b1;
b = 1'b0;
#20;
a = 1'b1;
b = 1'b1;
#20;
$finish;
end
endmodule Structural Modelling
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: alljobs.co.in
// Engineer: Team ( alljobs.co.in )
// Design Name: Half Adder
// Module Name: Half Adder
// Project Name: Half Adder using Verilog ( Structural Modelling )
// Language Used : Verilog HDL.
// Description: A design of Half adder has been simulated using Verilog HDL.
//////////////////////////////////////////////////////////////////////////////////
module half_adder(a,b,sum,cout);
input a,b;
output sum,cout; // sum and carry
xor x1(sum,a,b);
and a1(cout,a,b);
endmodule
//Testbench for halfadder
module half_adder_testbench;
reg a,b;
wire sum,cout;
half_adder h1(a,b,sum,cout);
initial begin
a = 1'b0;
b = 1'b0;
#20;
a = 1'b0;
b = 1'b1;
#20;
a = 1'b1;
b = 1'b0;
#20;
a = 1'b1;
b = 1'b1;
#20;
$finish;
end
endmodule Behavioural Modelling
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: alljobs.co.in
// Engineer: Team ( alljobs.co.in )
// Design Name: Half Adder
// Module Name: Half Adder
// Project Name: Half Adder using Verilog ( Behavioural Modelling )
// Language Used : Verilog HDL.
// Description: A design of Half adder has been simulated using Verilog HDL.
//////////////////////////////////////////////////////////////////////////////////
module half_adder(a,b,sum,cout);
input a,b;
output reg sum,cout; // sum and carry
always @(*)
begin
case ({a,b})
3'b00: sum = 0;
3'b01: sum = 1;
3'b10: sum = 1;
3'b11: sum = 0;
default : sum = 0;
endcase
case ({a,b})
3'b00: cout = 0;
3'b01: cout = 0;
3'b10: cout = 0;
3'b11: cout = 1;
default : cout = 0;
endcase
end
endmodule
//Testbench for halfadder
module half_adder_testbench;
reg a,b;
wire sum,cout;
half_adder h1(a,b,sum,cout);
initial begin
a = 1'b0;
b = 1'b0;
#20;
a = 1'b0;
b = 1'b1;
#20;
a = 1'b1;
b = 1'b0;
#20;
a = 1'b1;
b = 1'b1;
#20;
$finish;
end
endmodule RTL Design
Simulation Waveform ( Output )
