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# Full adder Verilog Code, Behavioral, Structural and Dataflow

Here is the Verilog code for Full adder. Here you are provided with the Verilog code of Full adder in three types – Behavioural Modelling, Structural Modelling and Dataflow Modelling.

All the three sets of Verilog code are provided with Testbench and RTL, Waveform of outputs.

Contents

A full adder is a combinational circuit that takes three input a,b,c and generate output as sum and carry. The full adder adds the three input producing two outputs sum and carry.

Let us say that the three input to the full adder are A,B,C then logical Expression for Sum will be (A)xor(B) xor (C) . And the logical expression for carry will be AB+BC+AC.

### Behavioural Modelling

```````timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: alljobs.co.in
// Engineer: Team ( alljobs.co.in )
// Project Name: Full Adder using Behavioural Modelling
// Language Used : Verilog HDL.
// Description: This is the verilog code for full adder using Behavioural Modelling
//////////////////////////////////////////////////////////////////////////////////
input a,b,c,
output reg sum,cout
);

always @(*)
begin
case ({a,b,c})
3'b000: sum = 0;
3'b001: sum = 1;
3'b010: sum = 1;
3'b011: sum = 0;
3'b100: sum = 1;
3'b101: sum = 0;
3'b110: sum = 0;
3'b111: sum = 1;
default : sum = 0;
endcase

case ({a,b,c})
3'b000: cout = 0;
3'b001: cout = 0;
3'b010: cout = 0;
3'b011: cout = 1;
3'b100: cout = 0;
3'b101: cout = 1;
3'b110: cout = 1;
3'b111: cout = 1;
default : cout = 0;
endcase
end
endmodule

reg a,b,c;
wire sum,cout;

initial begin
a = 1'b0;
b = 1'b0;
c = 1'b0;
#20;

a = 1'b0;
b = 1'b0;
c = 1'b1;
#20;

a = 1'b0;
b = 1'b1;
c = 1'b0;
#20;

a = 1'b0;
b = 1'b1;
c = 1'b1;
#20;

a = 1'b1;
b = 1'b0;
c = 1'b0;
#20;

a = 1'b1;
b = 1'b0;
c = 1'b1;
#20;

a = 1'b1;
b = 1'b1;
c = 1'b0;
#20;

a = 1'b1;
b = 1'b1;
c = 1'b1;
#20;

\$finish;
end
endmodule``````

### Structural Modelling

```````timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: alljobs.co.in
// Engineer: Team ( alljobs.co.in )
// Project Name: Full Adder using Structural Modelling
// Language Used : Verilog HDL.
// Description: This is the verilog code for full adder using Structural Modelling
//////////////////////////////////////////////////////////////////////////////////

input a,b,c,
output sum,cout
);
wire w1,c1,c2,c3,out1;
xor x1(w1,a,b);
xor x2(sum,w1,c);

and a1(c1,a,b);
and a2(c2,b,c);
and a3(c3,a,c);

or o1(out1,c1,c2);
or o2(cout,out1,c3);

endmodule

reg a,b,c;
wire sum,cout;

initial begin
a = 1'b0;
b = 1'b0;
c = 1'b0;
#20;

a = 1'b0;
b = 1'b0;
c = 1'b1;
#20;

a = 1'b0;
b = 1'b1;
c = 1'b0;
#20;

a = 1'b0;
b = 1'b1;
c = 1'b1;
#20;

a = 1'b1;
b = 1'b0;
c = 1'b0;
#20;

a = 1'b1;
b = 1'b0;
c = 1'b1;
#20;

a = 1'b1;
b = 1'b1;
c = 1'b0;
#20;

a = 1'b1;
b = 1'b1;
c = 1'b1;
#20;

\$finish;
end
endmodule``````

### Dataflow Modelling

```````timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: alljobs.co.in
// Engineer: Team ( alljobs.co.in )
// Project Name: Full Adder using DataFlow Modelling
// Language Used : Verilog HDL.
// Description: This is the verilog code for full adder using DataFlow Modelling
//////////////////////////////////////////////////////////////////////////////////

input a,b,c,
output sum,cout
);

assign sum = (a ^ b ^ c );
assign cout = (a & b ) | (b & c) | (a & c);

endmodule

reg a,b,c;
wire sum,cout;

initial begin
a = 1'b0;
b = 1'b0;
c = 1'b0;
#20;

a = 1'b0;
b = 1'b0;
c = 1'b1;
#20;

a = 1'b0;
b = 1'b1;
c = 1'b0;
#20;

a = 1'b0;
b = 1'b1;
c = 1'b1;
#20;

a = 1'b1;
b = 1'b0;
c = 1'b0;
#20;

a = 1'b1;
b = 1'b0;
c = 1'b1;
#20;

a = 1'b1;
b = 1'b1;
c = 1'b0;
#20;

a = 1'b1;
b = 1'b1;
c = 1'b1;
#20;

\$finish;
end
endmodule``````