*Implementation of 3:8 Decoder using Verilog. The Verilog Code of 3 :8 Decoder with Test bench , RTL Schematic and Waveform is provided below.*

**Contents**Show

## Decoder

A Decoder is a combinational logic circuit . It converts binary integer value to an associated pattern of output bits. A decoder has ‘*n’* input lines and 2* ^{n}* output lines.

Decoder gives output high depending on the combination of the inputs. It detects a particular code, and the output is the min terms of ‘n’ input variable lines, when enable is high.

Decoder has a wide variety of applications which includes, address decoding for CPU memory identification, instruction conversion from CPU to control signals, Code Converters, Logical Data Transfer, etc.

## 3:8 Decoder Truth Table

In a 3:8 decoder, 3 input lines and 8 output lines are required. The truth table of 3:8 decoder is given below ( Table 1) , where A,B,C are the input ; EN is enable line and Y7 to Y0 are the outputs of the 3:8 decoder.

EN | A | B | C | Y_{7} | Y_{6} | Y_{5} | Y_{4} | Y_{3} | Y_{2} | Y_{1} | Y_{0} |

0 | x | x | x | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |

1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |

1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |

1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |

1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |

1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |

1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |

1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |

1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |

## Boolean Expression for 3:8 Decoder

Y0 = A’B’C’

Y1= A’B’C

Y2= A’BC’

Y3= A’BC

Y4= AB’C’

Y5= AB’C

Y6= ABC’

Y7= ABC

## Verilog Code for 3:8 Decoder

The Verilog code for 3:8 Decoder is given below :

### RTL Design

```
`timescale 1ns / 1ps
module decoder_3_8(a, b, c, out);
input a,b,c;
output [7:0] out ;
assign out [0] = (~a&~b&~c) ;
assign out [1] =(~a&~b&c) ;
assign out [2] =(~a&b&~c);
assign out [3] = (~a&b&c);
assign out [4] = (a&~b&~c);
assign out [5] = (a&~b&c);
assign out [6] = (a&b&~c);
assign out [7] = (a&b&c);
endmodule
```

### Test Bench Code for 3:8 Decoder

The test bench check that each combination of input lines that connects the appropriate input to the output. The test bench code in Verilog for 3:8 Decoder is given below :

```
`timescale 1ns / 1ps
module test_decoder;
reg a, b,c;
wire [7:0] out;
decoder_3_8 DUT(a,b,c,out);
initial
begin
$monitor($time,"a=%b , b=%b , c=%b , out = %b" , a,b,c,out);
a=0 ; b=0 ;c=0 ;
# 100
a=0 ; b=0 ;c=1 ;
#100
a=0 ; b=1 ;c=0 ;
#100
a=1 ; b=1 ;c=1 ;
#100 $finish;
end
endmodule
```

## RTL Schematic Output

The RTL Schematic of the 3:8 Decoder is follows :

## Output of the Test Bench Simulation

The output of the Test bench simulation ( waveform ) is as follow :

## 3:8 Decoder FAQs

### Q. What is the number of input that can be applied to 3:8 Decoder ?

Ans. 3 input lines and 8 output lines.