D Flip Flop Verilog Code with Test bench and RTL

Design and Simulation of a D Flip Flop using verilog HDL. The result of simulation are also provided .

D Flip Flop

The D flip is also known as Delay Flip Flop. It is the delay device or a latch that is used to store 1 bit of the memory information.

The input data appears at the output at the end of the clock pulse. Thus, transfer of data from the input to the output is delayed and hence the name delay (D) flip-flop.

The DFF operates based on the rising edge or falling edge of the clock input. When the clock signal transitions from low to high (rising edge), the DFF stores the value of the data input D.

The stored value appears at the output Q. The complemented output ~Q always has the opposite value of the normal output Q.

Truth Table of D Flip Flop

A D flip-flop is a type of flip-flop circuit that stores a single bit of data. The output value of the flip-flop depends on the input value and the clock signal.

Here is the truth table for a D flip-flop:

In the table, D represents the input value, Q(t) represents the output value at time t, and Q(t+1) represents the output value at time t+1.

When the clock signal is low (0), the output value (Q) remains the same, regardless of the input value (D). When the clock signal is high (1), the output value (Q) changes to match the input value (D).

Characteristic Table of D Flip Flop

The characteristic table of a D flip-flop is a table that summarizes the behavior of the flip-flop in response to different inputs and clock signals.

The table shows the next state (Q_n+1) of the flip-flop based on the current state (Q_n), the input (D), and the clock signal (CLK). Here is the characteristic table for a D flip-flop:

In the table, X represents a “don’t care” condition, which means that the input value does not matter when the clock signal is low.

When the clock signal is high (1), the output value (Q) changes to match the input value (D).

When the input value is 0, the output value becomes 0 regardless of the previous state.

When the input value is 1, the output value becomes 1 regardless of the previous state.

Excitation Table of D Flip Flop

The excitation table of a D flip-flop is a table that shows the input D required to transition between different states (Q_n and Q_n+1). It is a useful tool for designing sequential circuits using flip-flops.

Characteristic equation of D Flip Flop : Q_n+1 = D

Here is the excitation table for a D flip-flop:

Verilog Code for D Flip Flop

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: alljobs.co.in
// Engineer: Team ( alljobs.co.in ) 
// Design Name: D Flip Flop
// Module Name: d_flip_flop
// Project Name: D Flip Flop
// Language Used : Verilog HDL.
// Description: A design of D Flip  Flop using Verilog HDL
//////////////////////////////////////////////////////////////////////////////////
module d_flip_flop (Q,D,clk,reset);
input D;
input clk;
input reset;
output reg Q;

always @(posedge clk or posedge reset)
  begin
    if (reset == 1'b1 )
        Q <= 1'b0;
    else
        Q <= D;
  end
endmodule        

// Testbench for D Flip Flop

module tb;
reg D;
reg clk;
reg reset;
wire Q;

d_flip_flop d1(Q,D,clk,reset);

initial 
  begin 
    clk = 1'b0;
    forever #20 clk = ~clk ;
  end
  
initial 
  begin
    reset = 1'b1;
    #40;
    reset = 1'b0;
    #40;
    D = 1'b0;
    #40;
    D = 1'b1;
    #40;
    
    $finish ;
  end
endmodule   

Simulation Waveform ( Output )

RTL Design