BCD to Excess 3 Conversion using verilog

Learn how to implement BCD to Excess 3 conversion using the Verilog hardware description language. This tutorial provides step-by-step instructions and code examples to help you understand the conversion process and apply it in your Verilog designs.

BCD Code

BCD (Binary Coded Decimal) is a coding scheme that represents each decimal digit with a 4-bit binary code. In BCD, each digit is represented by a unique 4-bit binary value from 0000 to 1001.

Here is the BCD code for decimal digits 0 to 9:

  • Digit 0: 0000
  • Digit 1: 0001
  • Digit 2: 0010
  • Digit 3: 0011
  • Digit 4: 0100
  • Digit 5: 0101
  • Digit 6: 0110
  • Digit 7: 0111
  • Digit 8: 1000
  • Digit 9: 1001

Each of these BCD codes represents the respective decimal digit in binary format. For example, BCD code 0011 represents the decimal digit 3, and BCD code 1001 represents the decimal digit 9.

Excess 3 Code

Excess-3 code, also known as XS-3 or 3XS, is a self-complementing BCD code that is obtained by adding 3 (0011 in binary) to each BCD digit. It is commonly used for arithmetic operations in digital systems.

Here is the Excess-3 code for decimal digits 0 to 9:

  • Digit 0: 0011
  • Digit 1: 0100
  • Digit 2: 0101
  • Digit 3: 0110
  • Digit 4: 0111
  • Digit 5: 1000
  • Digit 6: 1001
  • Digit 7: 1010
  • Digit 8: 1011
  • Digit 9: 1100

BCD to excess 3 conversion

To convert BCD (Binary Coded Decimal) to Excess-3 code, you can follow these steps:

  1. Take the BCD digit that you want to convert.
  2. Add 0011 (3 in binary) to the BCD digit.
  3. If the result exceeds 9 in BCD representation, adjust the result by adding 0110 (6 in BCD) to it.
  4. The final result is the Excess-3 code for the BCD digit.

Let’s go through an example to illustrate the steps:

Example: Convert BCD digit 0101 to Excess-3 code.

Start with the BCD digit 0101.

Add 0011 to 0101

0101 +

0011

——-

1000

——-

Since the result (1000) exceeds 9 in BCD, we need to adjust it by adding 0110

1000 +

0110

——

1110

——

The final result is 1110, which is the Excess-3 code for the BCD digit 0101.

So, the BCD digit 0101 is equivalent to the Excess-3 code 1110.

BCDExcess-3
00000011
00010100
00100101
00110110
01000111
01011000
01101001
01111010
10001011
10011100

To convert a BCD digit to Excess-3, simply look up the corresponding Excess-3 code in the table. For example, if you have the BCD digit 0101, you can find its Excess-3 equivalent by looking at the second row of the table, which gives you the code 1000.

`timescale 1ns / 1ps
//Implementaion of BCD to Excess3 by using DataFlow Modelling
module Bcd_excess3(b,e);
input [3:0] b;
output [3:0] e;
assign e[3]=b[3]|b[2]&b[1]|b[2]&b[0];
assign e[2]=~b[2]&b[1]|~b[2]&b[0]|b[2]&~b[1]&~b[0];
assign e[1]=b[1]&b[0]|~b[1]&~b[0];
assign e[0]=~b[0];
endmodule

//testbench

`timescale 1ns / 1ps

module Bcd_excess3_tb;
// Inputs
reg [3:0] b;
// Outputs
wire [3:0] e;
// Instantiate the Unit Under Test (UUT)
Bcd_excess3 uut (
.b(b),
.e(e)
);
initial begin
// Initialize Inputs
b=3'b0000;
#10;
b=4'b0001;
#10;
b=4'b0010;
#10;
b=4'b0011;
#10;
b=4'b0100;
#10;
b=4'b0101;
#10;
b=4'b0110;
#10;
b=4'b0111;
#10;
b=4'b1000;
#10;
b=4'b1001;
end
endmodule

This Verilog code implements a BCD to Excess-3 conversion using dataflow modeling. It consists of two modules: “Bcd_excess3” and “Bcd_excess3_tb” (testbench).

The “Bcd_excess3” module defines the BCD to Excess-3 converter. It has two ports: an input port “b” of size 4 bits representing the BCD digit, and an output port “e” of size 4 bits representing the Excess-3 code. The module uses the “assign” statements to specify the logic for each output bit of the Excess-3 code based on the input BCD bits.

The “Bcd_excess3_tb” module is the testbench module. It instantiates the “Bcd_excess3” module and connects its input and output ports. It also includes initial blocks to simulate the behavior of the BCD to Excess-3 conversion for different BCD inputs.

In the initial block of the testbench module, the input BCD digit “b” is initialized to different values (0 to 9) using the “#” delay operator. After each input value is assigned, there is a delay of 10 time units specified by “#10” to allow the simulation to observe the outputs before proceeding to the next input value.

By running this Verilog code in a simulation environment, you can observe the output “e” which represents the Excess-3 code corresponding to the input BCD digit “b”.

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