Implementation of 8 bit Up-Down Counter Using Verilog . The Verilog and Testbench code of 8 bit Up Down Counter is given below.
Up Down Counter
An up-counter counts events in increasing order. A down-counter counts stuff in the decreasing order. An up-down counter is a combination of an up-counter and a down-counter. It can count in both directions, increasing as well as decreasing.
8 bit Up Down Counter Verilog Code
The Verilog code for 8 bit Up Down Counter is given below:
RTL Design Verilog Code for 8 bit Up Down Counter
`timescale 1ns / 1ps module up_down_counter (clk, rst, UpDwn, count); input clk, rst; input UpDwn ; // UpDwn = 1 for Up counter and 0 for Down Counter output [7:0] count; reg [7:0] count = 0; // initially counter set to 0 always @ (posedge clk ) begin if (rst) count <= 0; end always @( posedge clk ) begin if (UpDwn == 1 && count >= 0 && count <= 255) count = count + 1; else if ( UpDwn == 0 && count >= 0 && count <=255) count = count - 1; end endmodule
Test Bench Code for 8 bit Up Down Counter
The test bench check that each combination of input lines that connects the appropriate input to the output. The test bench code in Verilog for 8 bit Up Down Counter is given below :
`timescale 1ns / 1ps module sim; reg CLK, RST, UpDwn; wire [7:0] COUNT; up_down_counter testcounter (.clk(CLK), .rst(RST), .UpDwn(UpDwn), .count(COUNT)); initial begin CLK = 0; forever #10 CLK = ~CLK; end initial begin RST = 1; #15; RST =0; #15; UpDwn = 0; #200; UpDwn = 1; #75; RST = 1; #15; RST=0; #15; $finish; end endmodule
RTL Schematic Output
The RTL Schematic of the 8 bit Up Down Counter is follows :
Output of the Test Bench Simulation
The output of the Test bench simulation ( waveform) is as follow :
8 bit Up Down Counter FAQs
Q. 8 bit counter will count upto which decimal number ?
Ans. An 8 bit counter will count till 255.