8:3 Encoder Verilog Code and Testbench Code with RTL Design

Implementation of 8:3 Encoder using Verilog. The Verilog Code of 8:3 Encoder with Test bench , RTL Schematic and Waveform is provided below.

Encoder

An Encoder is a combinational circuit that performs the reverse operation of Decoder.

It has maximum of 2^n input lines and ā€˜nā€™ output lines, hence it encodes the information from 2^n inputs into an n-bit code.

It will produce a binary code equivalent to the input, which is active High. Therefore, the encoder encodes 2^n input lines with ā€˜nā€™ bits.

8:3 Encoder Truth Table

In a 8:3 Encoder, 8 input lines and 3 output lines are required. The truth table of 8:3 Encoder is given below ( Table 1) , where Y7 to Y0 are the input ; EN is enable line and A0,A1,A2 are the outputs of the 8:3 Encoder.

ENY7Y6Y5Y4Y3Y2Y1Y0A2A1A0
0xxxxxxxxxxx
100000001000
100000010001
100000100010
100001000011
100010000100
100100000101
101000000110
110000000111
8:3 Encoder Truth Table

Verilog Code for 8:3 Encoder

The Verilog code for 8:3 Encoder is given below :

RTL Design

module encoder8_3( input [7:0]y, input en, output reg [2:0]a);

always @(*)
begin
if (en)
case (y)
8'b0000_0001: a=3'd0;
8'b0000_0010: a=3'd1;
8'b0000_0100: a=3'd2;
8'b0000_1000: a=3'd3;
8'b0001_0000: a=3'd4;
8'b0010_0000: a=3'd5;
8'b0100_0000: a=3'd6;
8'b1000_0000: a=3'd7;
endcase
else ;
end
endmodule

Test Bench Code for 8:3 Encoder

The test bench check that each combination of input lines that connects the appropriate input to the output. The test bench code in Verilog for 8:3 Encoder is given below :

`timescale 1ns / 1ps
module test_encoder;
reg [7:0]Y;
reg EN;
wire [2:0]A;
encoder8_3 uut(.y(Y), .en(EN),.a(A));
initial
begin
EN=1;
Y=8'h0_1;
#30;
Y=8'h0_2;
#30;
Y=8'h0_4;
#30;
Y=8'h0_8;
#30;
Y=8'h1_0;
#30;
Y=8'h2_0; #30;
Y=8'h4_0;
#30; Y=8'h8_0;
#30; 
$finish; 
end
endmodule

RTL Schematic Output

The RTL Schematic of the 8:3 Encoder is follows :

Output of the Test Bench Simulation

The output of the Test bench simulation ( waveform ) is as follow :

Test Bench Simulation Waveform for 8:3 Encoder Verilog Code

8:3 Encoder FAQs

Q. What is the number of output in 8:3 Encoder ?

Ans. There are 3 output lines in an 8:3 Encoder