# Verilog Code of 4 bit Adder using Full Adder RTL & Waveform

A 4 bit adder has two 4 bit inputs. The Verilog code for 4 bit adder using Full Adder. The RTL Design and the Waveform is also given after the code..

Contents

4 bit Adder is a digital circuit that has two four bit inputs and a 4 bit sum as output. It generates a 1 bit carry at the output. In the below code, the we have used the Full adder for making a a 4 bit adder. The Full adder has been instantiated four times in the main module. The Full adder takes two inputs as ‘a’ and ‘b’ and ‘cin’ as the third input. The equations of the Full adder are :-

Sum = (a xor b xor c) = a^b^c
Cout = (a and b ) or (b and cin ) or (cin and a ) = (a & b) | ( b & cin ) | ( cin & a )

The Verilog Code for the 4 Bit Adder using Full Adder is given below :

### RTL Design

``````module adder_four_bit(
output [3:0]sum,
output cout ,
input [3:0]a,b);

wire c1,c2,c3,c4;

full_3 ad0( .a(a[0]), .b(b[0]),.cin(0), .s(sum[0]), .cout(c1));
full_3 ad1( .a(a[1]), .b(b[1]),.cin(c1), .s(sum[1]), .cout(c2));
full_3 ad2( .a(a[2]), .b(b[2]),.cin(c2), .s(sum[2]), .cout(c3));
full_3 ad3( .a(a[3]), .b(b[3]),.cin(c3), .s(sum[3]), .cout(c4));
assign cout= c4;
endmodule

module full_3(a,b,cin,s,cout);
input a,b,cin;
output s, cout;
assign s=a^b^cin;
assign cout = (a&b) | (b&cin) | (cin&a);
endmodule
``````

### Test Bench

The test bench check that each combination of select lines connects the appropriate input to the output. The test bench code in Verilog for 4 Bit Adder using Full Adder is given below :

```````timescale 1ns / 1ps
reg [3:0] a;
reg [3:0] b;

wire [3:0] s;
wire cout;

initial
begin
a=4'b0000;
b=4'b0001;

#30
a=4'b0001;
b=4'b0001;

#30
a=4'b0010;
b=4'b0001;

#30;
a=4'b0100;
b=4'b0101;
#30;
a=4'b1100;
b=4'b1101;
#30;
\$finish;

end
endmodule
``````

## Output of the Test Bench Simmulation

The output of the Test bench simulation ( waveform) is as follow :