1011 Sequence Detector – Overlapping/Non Overlapping Verilog

Implementation of 1011 Sequence Detector. Here is the Verilog code for 1011 sequence Detection with test bench. It consists of overlapping and non-overlapping concepts for detection of 1011 sequence in the input stream of bits. Here the both Moore and mealy machine codes are provided for 1011 sequence detection.

Sequence Detector 1011

Sequence Detector 1011 detects the presence of the input bits in the sequence “1011”. It displays an output with logic high ( 1 ) when the sequence “1011” is detected. The four types of sequence detector 1011 provided on this page are :

  • 1011 Sequence detector Overlapping – Mealy Machine and Moore Machine
  • 1011 Sequence detector Non-Overlapping – Mealy Machine and Moore Machine

1. Sequence Detector 1011 Mealy Machine Non – Overlapping

A) State Diagram

B) Verilog Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: alljobs.co.in
// Engineer: Team ( alljobs.co.in ) 
// Design Name: 1011 Sequence Detector
// Module Name: sequence_detector
// Project Name: Mealy Sequence Detector for 1011 
// Language Used : Verilog HDL.
// Description: This is sequence detector  verilog code. 
//This verilog code is made to detect the 1011 Non Overlapping sequence.
//////////////////////////////////////////////////////////////////////////////////

// Overlapping sequence 1011 verilog code 
module sequence_detector_non_overlapping_mealy_1011( clock, machine_reset,in_seq,sequence_detected);
input clock;
input machine_reset;
input in_seq; 
output reg sequence_detected;

parameter State0 = 0, State1=1, State2=2, State3=3;
reg [1:0]next_state,present_state;

always @(posedge clock)
    begin
        if (machine_reset) begin
            present_state<=State0;
            sequence_detected = 1'b0; end
        else 
            present_state<=next_state;
            
    end
    
always @(*)
    begin
       case ( present_state)
         State0 : next_state = in_seq ? State1:State0; 
         State1 : next_state = in_seq ? State1:State2;
         State2 : next_state = in_seq ? State3:State0;
         State3 : next_state = in_seq ? State0:State1;
         default : next_state = State0;
       endcase
    end
    
always @(*)
    begin
      case ( present_state)
          State0 : sequence_detected = 1'b0;
          State1 : sequence_detected = 1'b0;
          State2 : sequence_detected = 1'b0;
          State3 : sequence_detected = in_seq ? 1 : 0 ;
          default : sequence_detected =1'b0;
       endcase          
     end    
endmodule

C) Test Bench Code

//Testbench
`timescale 1ns / 1ps
module sequence_test_bench;
reg clock;
reg machine_reset;
reg in_seq; 
wire  sequence_detected;

sequence_detector_non_overlapping_mealy_1011 seq( clock, machine_reset,in_seq,sequence_detected);

initial begin 
clock = 1'b1;
forever #5 clock = ~clock;
end

initial begin
#5;
machine_reset = 1'b1;
#10; 
machine_reset = 1'b0;
#5;
in_seq = 1'b1;
#8;
in_seq = 1'b0;
#8;
in_seq = 1'b1;
#8;
in_seq = 1'b1;
#8;
in_seq = 1'b0;
#8;
in_seq = 1'b0;
#8;
in_seq = 1'b1;
#8;
in_seq = 1'b0;
#8;
in_seq = 1'b1;
#8;
in_seq = 1'b1;
#12;
in_seq = 1'b0;
#8;
in_seq = 1'b1;
#8;
in_seq = 1'b1;
#8;
in_seq = 1'b1;
#8;
$finish;
end
endmodule

D) RTL Design

E) Output Waveform