1010 Sequence Detector Moore, Mealy Verilog Code Test bench

Implementation of 1010 Sequence Detector. Here is the Verilog code for 1010 sequence Detection with test bench. It consists of overlapping and non-overlapping concepts for detection of 1010 sequence in the input stream of bits.

1010 Sequence Detector

1010 Sequence Detector detects the presence of the input bits in the sequence “1010”. It displays an output with logic high ( 1 ) when the sequence is detected.

The four types of 1010 sequence detector are –

  • 1010 Sequence detector Overlapping – Mealy Machine
  • 1010 Sequence detector Overlapping – Moore Machine
  • 1010 Sequence detector Non-Overlapping – Mealy Machine
  • 1010 Sequence detector Non-Overlapping – Moore Machine

1. Sequence Detector 1010 Overlapping Mealy Machine

A) State Diagram

sequence detector 1011
1010 Sequence Detection State Diagram

B) Verilog Code for 1010 Overlapping Sequence Detector using Mealy Machine

Verilog Code for the sequence detector 1010 Overlapping using a mealy machine is provided below :

//////////////////////////////////////////////////////////////////////////////////
// Company: alljobs.co.in
// Engineer: Team ( alljobs.co.in ) 
// Design Name: 1010 Sequence Detector
// Module Name: sequence_detector
// Project Name: Mealy Sequence Detector for 1010 
// Language Used : Verilog HDL.
// Description: This is a sequence detector Verilog code. This Verilog code is made to detect the 1010 sequence.
//////////////////////////////////////////////////////////////////////////////////

// Overlapping sequence 1010 verilog code Mealy Machine
`timescale 1ns / 1ps
module sequence_detector_overlapping_mealy( clk, rst,data_in,data_out);
input clk;
input rst;
input data_in; 
output reg data_out;

parameter S0 = 0, S1=1, S2=2, S3=3;
reg [1:0]ns,ps;

always @(posedge clk)
    begin
        if (rst) begin
            ps<=S0;
            data_out = 1'b0; end
        else 
            ps<=ns;
            
    end
    
always @(*)
    begin
       case ( ps)
         S0 : ns = data_in ? S1:S0; 
         S1 : ns = data_in ? S1:S2;
         S2 : ns = data_in ? S3:S0;
         S3 : ns = data_in ? S1:S2;
         default : ns = S0;
       endcase
    end
    
always @(*)
    begin
      case ( ps)
          S0 : data_out = 1'b0;
          S1 : data_out = 1'b0;
          S2 : data_out = 1'b0;
          S3 : data_out = data_in ? 0 : 1 ;
          default : data_out =1'b0;
       endcase          
     end    
endmodule

C) Testbench Code for 1010 Overlapping Sequence Detector using Mealy Machine

Test Bench Code for the sequence detector 1010 Overlapping using a mealy machine is provided below :

`timescale 1ns / 1ps
module sequence_test_bench;
reg clk;
reg rst;
reg data_in; 
wire  data_out;

sequence_detector_overlapping_mealy seq( clk, rst,data_in,data_out);

initial begin 
clk = 1'b1;
forever #5 clk = ~clk;
end

initial begin
#5;
rst = 1'b1;
#10; 
rst = 1'b0;
#5;
data_in = 1'b1;
#8;
data_in = 1'b0;
#8;
data_in = 1'b1;
#8;
data_in = 1'b0;
#8;
data_in = 1'b1;
#8;
data_in = 1'b0;
#8;
data_in = 1'b1;
#8;
data_in = 1'b1;
#8;
data_in = 1'b0;
#8;
data_in = 1'b1;
#12;
data_in = 1'b0;
#8;
data_in = 1'b1;
#8;
data_in = 1'b0;
#8;
data_in = 1'b1;
#8;
$finish;
end
endmodule

D) RTL Design Output

E) Output of Test Bench Simulation (Waveform)