Implementation of 1:8 Demultiplexer . The Verilog Code for 1:8 Demultiplexer with the Testbench code and RTL Schematic and Test Bench Simulation Waveform is provided here.
Demultiplexer
A Demultiplexer is also called Demux, or data distributor and its operation is quite opposite to a multiplexer because it is an inverse to the multiplexer.
The multiplexer is a many-to-one circuit whereas the Demultiplexer is a one-to-many circuit. By using Demultiplexer, the transmission of data can be done through one single input to a number of output data lines.
Generally, Demultiplexers are used in decoder circuits and Boolean function generators
1:8 Demultiplexer Truth Table
The Truth Table for a 1:8 Demultiplexer is given below. ( Where A is the Input and , S0,S1,S2 are the three select lines and Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7 are the eight outputs of 1:8 Demultiplexer.
A | S2 | S1 | S0 | Y0 | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 |
1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Boolean Expression for 1:8 Demultiplexer
Y0 = A (S2)'(S1)'(S0)’
Y1 = A (S2)'(S1)'(S0)
Y2 = A (S2)'(S1)(S0)’
Y3 = A (S2)'(S1)(S0)
Y4 = A (S2)(S1)'(S0)’
Y5 = A (S2)(S1)'(S0)
Y6 = A (S2)(S1)(S0)’
Y7 = A (S2)(S1)(S0)
Verilog Code 1:8 Demultiplexer
The Verilog code for 1:8 Demultiplexer is given below :
RTL Design
module demux_1_8(y,s,a);
output reg [7:0]y;
input [2:0]s;
input a;
always @(*)
begin
y=0;
case(s)
3'd0: y[0]=a;
3'd1: y[1]=a;
3'd2: y[2]=a;
3'd3: y[3]=a;
3'd4: y[4]=a;
3'd5: y[5]=a;
3'd6: y[6]=a;
3'd7: y[7]=a;
endcase
end
endmodule
Test Bench Code for 1:8 Demultiplexer
The test bench check that each combination of input lines that connects the appropriate input to the output. The test bench code in Verilog for 1:8 Demultiplexer is given below :
module test_demux;
reg [2:0]S;
reg A;
wire [7:0]Y;
demux_1_8 mydemux(.y(Y), .a(A), .s(S));
initial begin
A=1;
S=3'd5;
#30;
A=0;
S=3'd1;
#30;
A=1;
S=3'd1;
#30;
S=3'd6;
#30;
S=3'd0;
#30;
$finish;
end
endmodule
RTL Schematic Output
The RTL Schematic of the 1:8 Demultiplexer is follows :
Output of the Test Bench Simulation
The output of the Test bench simulation ( waveform ) is as follow :
1:8 Demultiplexer FAQs
Q. What is the number of select lines in the 1:8 Demultiplexer ?
Ans. Three Select lines are required in 1:8 Demultiplexer.